{"id":70,"date":"2019-03-11T08:45:28","date_gmt":"2019-03-11T13:45:28","guid":{"rendered":"http:\/\/blog.siliconics.ca\/?p=70"},"modified":"2019-03-11T13:54:04","modified_gmt":"2019-03-11T18:54:04","slug":"intel-announces-tweaks-to-22ffl-process-for-rf-mram-at-iedm18-part-1","status":"publish","type":"post","link":"http:\/\/blog.siliconics.ca\/index.php\/2019\/03\/11\/intel-announces-tweaks-to-22ffl-process-for-rf-mram-at-iedm18-part-1\/","title":{"rendered":"Intel announces tweaks to 22FFL process for RF, MRAM at IEDM18 – Part 1"},"content":{"rendered":"\n

At IEDM last year, Intel\ngave a half-dozen papers on various topics, including two on their 22FFL SoC\nprocess aimed at low power IoT and mobile products. The first (14.1) was an\ninvited presentation on \u201cIntel 22nm\nFinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit\nDesign Optimization for FinFET Technology<\/em>\u201d, and the second (18.1)\nintroduced \u201cMRAM as Embedded Non-Volatile\nMemory Solution for 22FFL FinFET Technology<\/em>\u201d. I had planned to cover the\ntwo papers in one article, but it expanded to the point where it made more sense\nto split it into two parts. So, here is the first part on the RF enhancements\nto the 22FFL process.<\/p>\n\n\n\n

Part\n1 \u2013 Initial 22FFL and RF Enhancements<\/strong><\/p>\n\n\n\n

Initial\n22FFL Announcements<\/strong><\/p>\n\n\n\n

Mark Bohr announced the\n22FFL process at the Technology and Manufacturing Day (TMD) at the end of March\nin 2017. At the time they said that it was \u201cFully RF design enabled\u201d, but gave\nno more details, and MRAM as an option was not mentioned.<\/p>\n\n\n\n

More details were given at IEDM 2017 [1], but again no discussion of MRAM. The basic process details as stated at TMD were: <\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

The raw dimensions, as you\u2019d\nexpect, are in between the 14-nm and 22-nm processes. The logic transistor\nimages shown at IEDM17 indicate that 22FFL is based on the 14-nm technology,\nsince we no longer have the tapered fins, and the punch-stop seal is present: <\/p>\n\n\n\n

\"\"
TEM images of logic transistor ; parallel to gate (left) and parallel to fin (right) <\/figcaption><\/figure>\n\n\n\n

The fins are still\ndouble-patterned, but the gate and metal are single-patterned, and the SRAM\ncell size puts it close to the 22-nm node. If we use the 45 nm fin pitch as a\ncalibration, the fin heights come out at 36 \u2013 38 nm, and fin width ~7 nm,\ngiving a gate width of 80 \u2013 85 nm. That is similar to the 22-nm fins and compares\nwith ~42 nm fin height at 14-nm. <\/p>\n\n\n\n

\nThe base process combines high-performance, low power, and ultra-low\npower logic, analog, and high-voltage (HV) transistors [1]:\n\n\n\n<\/p>\n\n\n\n

\"\"<\/figure>\n\n\n\n

\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\nThe high-performance\ntransistors show 57%\/87% higher NMOS\/PMOS drive current compared to the 22-nm\ntechnology. The use of the punch-stop diffusion means that the fins are\nundoped, so Vt is set by adjusting gate length and work function for the\nvarious devices. As shown in the table, the HV transistors have thicker gate\noxide and longer gate lengths.\n\n\n\n<\/p>\n\n\n\n

\"\"
TEM images of 1.8 V I\/O transistor; parallel to gate (left) and parallel to fin (right) <\/figcaption><\/figure>\n\n\n\n

When it comes to the RF capabilities,\na device with optimized layout was developed and showed fT<\/sub>\/fMAX<\/sub>\nof 230 GHz\/284 GHz and 238 GHz\/242 GHz for NMOS and PMOS respectively, with a\n32 nm gate length.<\/p>\n\n\n\n

Other SoC features in 22FFL are high resistance substrate, deep N-well isolation, precision resistors, MIM capacitors, and high-Q inductors. The relaxed metal pitch of the single-patterned back end results in reduced parasitics at the sacrifice of density \u2013 a good tradeoff for RF SoCs. <\/p>\n\n\n\n

RF Modifications<\/strong><\/p>\n\n\n\n

In this year’s RF paper [2], five flavours of transistors were offered;
nominal and low VT<\/sub> low-leakage, nominal and low VT<\/sub> high-density, and high-performance (HP). A drawback of FinFETtechnology is the increased lateral parasitic capacitance given by the extra gate material between the fins – as the poly pitch gets tighter, the capacitance increases, lowering fT<\/sub>, without increasing transconductance (gm<\/em>). This effectively means that the 22-nm process is better suited to RF applications than smaller or larger nodes.
<\/p>\n\n\n\n

\"\"
fT and fMAX vs process node: both peak around 20 ~ 25 nm<\/figcaption><\/figure>\n\n\n\n

A known phenomenon of finFETs is self-heating, where the fin temperature increases while conducting current, made worse by the thermal isolation of the fin. This impacts temperature-dependent parameters such as mobility and threshold voltage, resulting in performance degradation, and endangering device and interconnect reliability. The effect can be reduced by operating at lower current densities or supply voltages, potentially trading off performance for reliability. Since finFETS have better channel control than planar devices, we can keep strong drive current at low supply voltages, enabling high performance low-voltage designs without reducing reliability.
Another feature of finFETs is the additional vertical component of the gate resistance; this non-linear resistance allows the designer to optimize devices for fT or fMAX by tuning the configuration of fins and gate legs. <\/p>\n\n\n\n

\"\"
Schematic of finFET gate capacitance and resistance structure: horizontal (Rh) and vertical (Rv) resistances surrounding fin structures<\/figcaption><\/figure>\n\n\n\n

As a result, the HP NMOS fT has been pushed over 300 GHz, and the fMAX beyond 450 GHz, and PMOS to just under 300 GHz.<\/p>\n\n\n\n

\"\"
RF performance of HP transistors optimized for peak fT (left) and peak fMAX (right)<\/figcaption><\/figure>\n\n\n\n

The Intel paper does not give any data on the number of fins or gate legs for the devices described, but I found this simulation [3] based on Intel\u2019s published figures for their initial 22-nm process, i.e. with trapezoidal fins [4]. Using the same effective gate width, it gives an indication of the influence of the fin and gate finger configuration on RF performance. One presumes, looking at these fT numbers (fT >750 GHz for 20 fins), that there are significantly fewer fins in the 22FFL transistors quoted, with an fT of ~300 GHz.
<\/p>\n\n\n\n

\"\"
fT vs. numbers of fingers and fins; the finger number for each different fin number is adjusted to give the same device width [3].<\/figcaption><\/figure>\n\n\n\n

  <\/p>\n\n\n\n

For low-noise amplifier (LNA) designs, noise matching and power matching can be tuned by regulating the input impedance, adjusting the number of fins for a particular device sizing.
Below we see three cases of fin configuration, maintaining total device size by changing the number of gate fingers. The maximum available gain Gmax<\/em> and the minimum noise figure NFmin<\/em> vary with the fin number, so the LNA figure of merit (FoM = Gmax<\/em> \u2013 NFmin<\/em> ) also varies. In this case the FoM maximum is in 4- or 6-fin devices; Gmax<\/em> and NFmin<\/em> were normalized to the Gmax <\/em>and NFmin<\/em> of a 2-fin device.<\/p>\n\n\n\n

\"\"
Device sizing for optimum LNA FoM; 4 or 6-fin devices reach highest equivalent FoM at ~0.3mA\/um current density.<\/figcaption><\/figure>\n\n\n\n

While the above figure shows relative NFmin<\/em>, other work [5] shows that the noise figure is below 2 dB up to 73 GHz, suitable for a mm-Wave receiver LNA.<\/p>\n\n\n\n

\"\"
Plot of simulated NFmin<\/em> vs. frequency [5]<\/figcaption><\/figure>\n\n\n\n

When it comes to flicker (1\/f) noise, FinFETs have inherently lower drain-induced barrier lowering (DIBL) compared with planar transistors, and we have the punch-through-stop diffusion in 22FFL, so there are no VT adjust implants, and likely no halo implant, both of which help generate flicker noise. By comparison, an equivalent planar transistor is at least 10x greater.<\/p>\n\n\n\n

\"\"
Flicker noise of 22FFL high performance logic transistors [1]<\/figcaption><\/figure>\n\n\n\n

We will see what products come out in the RF-enhanced 22FFL, but with 5G looming up and Intel getting design wins in iPhones, there does seem to be potential, and Intel has clearly been working on the technology.<\/p>\n\n\n\n

References<\/p>\n\n\n\n

  1. B. Sell, et al., \u201c22FFL: A High Performance and Ultra Low Power FinFET Technology for Mobile and RF Applications\u201d, IEDM Tech. Dig. 2017, pp. 685 \u2013 688.<\/li>
  2. H.-J. Lee, et al., \u201cIntel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology\u201d, IEDM Tech. Dig. 2018, pp. 316 \u2013 319.<\/li>
  3. T. An, et al., \u201cPerformance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance\u201d, Journal of Semiconductor Technology and Science, vol.14, no.5, Oct. 2014.<\/li>
  4. C. Auth, et al., \u201cA 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors,\u201d Proc. VLSI Tech. 2012, pp. 131-132.<\/li>
  5. S. Callender, et al., \u201cFinFET for mmWave \u2013 Technology and Circuit Design Challenges\u201d, Proc. BCICTS 2018, pp. 168 \u2013 173.<\/li><\/ol>\n","protected":false},"excerpt":{"rendered":"

    At IEDM last year, Intel gave a half-dozen papers on various topics, including two on their 22FFL SoC process aimed at low power IoT and mobile products. The first (14.1) was an invited presentation on \u201cIntel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology\u201d, and the […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7,6,14,11],"tags":[10,8,9],"class_list":["post-70","post","type-post","status-publish","format-standard","hentry","category-22-nm","category-cmos","category-conferences","category-rf","tag-finfet","tag-intel","tag-rf"],"_links":{"self":[{"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/posts\/70","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/comments?post=70"}],"version-history":[{"count":25,"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/posts\/70\/revisions"}],"predecessor-version":[{"id":117,"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/posts\/70\/revisions\/117"}],"wp:attachment":[{"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/media?parent=70"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/categories?post=70"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/blog.siliconics.ca\/index.php\/wp-json\/wp\/v2\/tags?post=70"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}